As the number of devices in a very large scale integrated (VLSI) circuit chip increases, the individual transistor devices which form its component elementary logic circuits, occupy areas of the chip on the order of a few square microns or less. The quantity of charge which is transferred between field effect transistor devices of that size while carrying out normal switching operations is such that the circuits are very susceptible to electrostatic and even radiation-induced perturbations. In many systems such perturbations, even when they are only transient in nature, may cause or trigger large scale error-correcting processes to be initiated, such as system re-booting. Such error correcting processes, in turn, may cause unnecessary processing delays especially in the case of transient errors, where by the time the system has been re-booted, a transient error has been long gone.
Computer systems may be protected from faults by using parity error protection or error correcting code (ECC) techniques. A double error detection ECC will detect and correct all single bit errors, including transient and "stuck-at" faults, as well as all two-bit errors. However, ECC is quite expensive since even for a single error correcting code, a large number of bits will be required. Parity techniques on the other hand are relatively inexpensive but can serve for error detection only. As chip densities increase and newer technologies are implemented, it is expected that the occurrence of transient errors will increase.
Thus there is a need for a method and apparatus which is cost effective and which includes improved immunity to transient errors thereby allowing continued data processing operations with only minimal modification to accommodate the error checking function while minimizing unnecessary recycling in response to transient errors.